Job Description

Job description

• MediaTek’s advanced Memory Design team in San Jose is looking for a high-performance senior memory design engineer and architect to define and architect memory designs and circuits for next generation ASICs for Cloud AI and Data center applications.
• Primary job responsibilities include close collaboration with tier-1 ASIC customers in North America to define and enable System Technology Co-optimizations (STCO/DTCO) for embedded and 3D memory architectures and circuits in advanced nodes for high performance compute ASIC’s targeting Cloud AI, Data Center Networking, Automotive and other Enterprise ASIC applications.
• Understand requirements for multi-die chiplet based solutions for memory and compute dies on a single package in 2.5D and 3D architectures.
• Optimize memory performance and bandwidth to enhance system PPA on 2.5D and 3D architectures.
• Understand pros and cons of Through Silicon Via (TSV) based 3D stacking architectures for adoption in high performance memory and compute on single package solutions.
• Collaborate closely with product and architecture teams to define, design, and develop high performance customized semiconductor memories including SRAM, CPU caches with different PPA requirements for Cloud AI and Automotive.
• Mentor, guide, and direct other designers, while being hands-on in digital circuit design, especially targeting memories.
• Highly organized and independent design engineer who can multi-task and closely collaborate with worldwide design and CAD teams.

Job requirements:

• 15+ years of hands-on experience in design of embedded memories (SRAM, TCAM) for high performance processors or ASICs in advanced nodes (3nm/5nm)
• Knowledge of TSVs for silicon-to-silicon communication and chiplet based solutions.
• Understanding of HBM die data path and bandwidth/interface requirements.
• Good knowledge of advanced packaging techniques as applicable to advancing memory and compute performance across multi-chip solutions on single package.
• Strong track record of offering innovative solutions (papers, patents), good understanding of technology roadmap and market for embedded memories.
• Strong understanding of Digital Circuit design techniques in FinFet technologies.
• Expert in SRAM/DRAM/HBM based designs.
• Exposure to complete design cycle of SRAM memory and compiler development
• Supervise layout engineers and review layout for optimality.
• Have the ability to come up with comprehensive design verification plans, silicon bring-up plans for high-performance embedded memories.
• Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA, FINESIM), STA such as PrimeTime and Nanotime.
• Experience with LEC tools (ESPCV)
• Ability to review and coordinate layout activities
• Silicon debug and bring up experience is required.
• Working knowledge of scripting in Perl/Python
• Willingness to collaborate closely with cross functional teams across the globe.

Salary range: $190,000 - $260,000

Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Paid time off (PTO), Parental leave, 401K and more.

MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.

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